1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a storage circuit or an information holding circuit composed of a transistor, a soft error rate calculation method and a program of the same, and a design method and a design apparatus of the same.
2. Description of Related Art
A soft error is one of the problems caused by scaling process of recent semiconductor devices. In a narrow sense, a soft error of semiconductor devices is a temporal defect that causes the “inversion” of information due to the loss of charges that are accumulated in a storage node by radiation. Combined with the trend for low-voltage circuit design, the soft error will become a serious problem.
One measure against this problem is to improve the resistance to soft errors by adding a capacitance to a storage node. However, with the recent development of small memory cells, it is difficult to add a large capacitance in a simple process. In addition, it is unable to add a capacitance that is large enough to prevent soft errors to a high-speed SRAM because of the operation speed.
Besides the addition of a capacitance, another measure against to soft errors is to optimize the impurity concentration profile of a cell node diffusion layer or a substrate (well). One method for optimizing the impurity concentration profile of a cell node diffusion layer or a substrate (well) is to reduce electrons and positive holes to enter a cell node diffusion layer. A typical method is to form a well or a barrier layer in a well. However, a considerable amount of prototyping is required to determine the optimization conditions.
In the present circumstances, products are manufactured by combining various kinds of such measures, rather than employing any one of them. Therefore, a soft error rate SER cannot be determined until prototyping a product or TEG (Test Element Group).
The trend for SER of released SRAM varies by publisher. For example, P. Hazucha, et al., “Neutron Soft Error Rate Measurements in a 90-nm CMOS Process and Scaling Trends in SRAM from 0.25-μm to 90-nm Generation”, 2003 IEEE International Electron Devices Meeting TECHNICAL DIGEST, pp. 523-526 (FIG. 16) (Document 1) describes that SER deteriorates (e.g. FIT value increases) by scaling process when a comparison is made per unit bit rate in each generation. On the other hand, Soon-Moon Jung, et al., “Soft Error Immune 0.46 μm2 SRAM Cell with MIM Node Capacitor by 65 nm CMOS Technology for Ultra High Speed SRAM”, 2003 IEEE International Electron Devices Meeting Technical Digest, pp. 289-292 (FIG. 9) (Document 2) and Ethan H. Cannon, et al., “SRAM SER in 90, 130 and 180 nm Bulk and SOI Technologies”, 2004 IEEE International Reliability Physics Symposium, pp. 300-304 (FIG. 1) (Document 3) describe that SER generally improves (e.g. FIT value decreases) by scaling process. The reason of such a difference is probably a difference in voltage (node voltage) setting and cell size in SRAM in each generation.
In this background, it becomes increasingly important to accurately estimate SER of a scaling process device during the design phase. Simulation has been used for the estimation of SER.
Generally, the soft error simulation requires product process information, mask layout information, circuit information, nuclear reaction model and soon, and therefore there is a problem that it is only engineers with a good knowledge of a simulator (i.e. those who developed a simulator) who can use the simulator. An example of the simulation is described in Japanese Unexamined Patent Application Publication No. 2004-251813 (Ibe et al.). Ibe et al. discloses a technique of performing a simulation and feeding back a simulation result to product design, and a method of evaluating the simulation.
Further, there is a technique of performing a simulation using specific information as a parameter and putting results into a table, so that SER can be calculated simply by inputting a parameter. For example, Y. Tosaka, et al., “Simple Method for Estimating Neutron-Induced Soft Error Rates Based on Modified BGR Model”, IEEE Electron Device Letters, VOL. EDL-20, NO. 2, pp 89-91, 1999 (Document 4) describes table model data using a MBGR method.
The use of the table model that is described in the above document enables easy calculation of SER with a calculator or the like. However, when using this table model, it is necessary to obtain, by simulation, a value (sensitive depth) d that is calculated from the relationship of cell size and depth with charges (critical charges) Qc required for the inversion of a cell node and a depletion layer W taken into consideration. Therefore, under the present circumstances, the use of a simulator is still needed in order to estimate SER during the design phase. Further, the verification of the accuracy of simulation is also needed. If SER can be estimated accurately without the use of a simulation during the phase of system design, it would be possible to take measures against soft errors in a system and thus offer convenience.